VLSI (VHDL / VERILOG) Final Year Projects

Final Year Projects offers the latest VLSI (VHDL / VERILOG) Final Year Projects for BE, B.Tech, M.Tech, and engineering students. Get complete project solutions with source code, documentation, research support, and expert guidance. Learn and complete your project easily while gaining practical experience. Choose from our handpicked list of IEEE project titles to start your project today.

S.NoIEEE PROJECT TITLES  
FY5VL1Advanced Encryption Standard Algorithm With Optimal S-Box and Automated Key Generation
FY5VL2Design and Verification of DDR SDRAM Memory Controller Using SystemVerilog
FY5VL3Fast Binary Counters and Compressors Generated by Sorting Network
FY5VL4Area?Delay and Energy Efficient Multi-Operand Binary Tree Adder
FY5VL5High-Speed Efficient Carry Adder Using Reversible Gates
FY5VL6Design of a Reversible Floating-Point Square Root Using Modified Non-Restoring Algorithm
FY5VL7Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators
FY5VL8Design of Power Efficient Posit Multiplier
FY5VL9Design and Analysis of High-Speed Wallace Tree Multiplier Using Parallel Prefix Adders
FY5VL10Efficient Design for Fixed-Width Adder Tree
FY5VL11Chaos-Based Bitwise Dynamical Pseudorandom Number Generator on FPGA
FY5VL12Low-Power Approximate Unsigned Multipliers With Configurable Error Recovery
FY5VL13Borrow Select Subtractor for Low Power and Area Efficiency
FY5VL14Energy-Quality Scalable Adders Based on Non-Zeroing Bit Truncation
FY5VL15Double MAC on a DSP Boosting the Performance of CNNs on FPGAs
FY5VL16Ultra-Low-Voltage GDI-Based Hybrid Full Adder Design
FY5VL17Design of Area-Efficient and Low-Power 4-Bit Multiplier Using Full-Swing GDI Technique
FY5VL18Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis
FY5VL19Novel High-Speed Vedic Multiplier Proposal Using Quaternary Signed-Digit System
FY5VL20Unbiased Rounding for HBF Floating-Point Addition
FY5VL21A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design
FY5VL22FPGA Implementation of an Improved Watchdog Timer for Safety-Critical Applications
FY5VL23MAES: Modified Advanced Encryption Standard for Resource-Constrained Environments
FY5VL24Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
FY5VL25DLAU: A Scalable Deep Learning Accelerator Unit on FPGA

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